The present invention relates to a recording and reproducing timing generating apparatus which controls the phase of a sampling clock signal of reproducing data by a sampling servo system in which a servo pattern including a clock mark is recorded to a memory medium at a constant interval, and which controls a delay time of the sampling clock signal based on the voltage level of a reproducing signal sampled by the sampling clock signal.
For example, in a conventional magnetooptic disk drive unit, etc., the phase of a sampling clock signal of reproducing data is controlled by a sampling servo system. A sampling signal for measuring a phase delay amount is recorded in a predetermined region at a data-recording time. A delay time of the sampling clock signal is controlled on the basis of a reproducing voltage level of the sampling signal. Such a phase controller is proposed in Japanese Patent Application Laying Open (KOKAI) No. 63-244448 as a phase control circuit.
In general, an optical disk has a plurality of servo areas separated from a data area with respect to one track. As shown in FIG. 32, in each of these servo areas, a set of wobble pits and a clock pit are formed as a pre-format at a constant interval along a track to detect a tracking error. The set of wobble pits are formed such that the track is located between these wobble pits. The clock pit is formed to detect timings for recording and reproducing data.
The conventional recording and reproducing timing generating apparatus used in an optical disk drive unit and generating a recording/reproducing clock signal for recording and reproducing information with respect to the optical disk will next be described with reference to FIG. 33.
In FIG. 33, a reproducing signal S1 is reproduced by an unillustrated optical pickup device and is inputted to an A/D converter 101 and a pulsating circuit 102. The reproducing signal S1 inputted to the A/D converter 101 is then A/D-converted by a recording/reproducing clock signal described later.
The reproducing signal S1 inputted to the pulsating circuit 102 is changed by the pulsating circuit 102 to a pulse signal S2 corresponding to a bottom (or peak) position of the reproducing signal S1. This pulse signal S2 is inputted to a synchronous signal generating circuit (which is called a PLL circuit in the following description) 103 for making a recording/reproducing clock signal synchronized with the pulse signal S2.
The pulse signal S2 inputted to this PLL circuit 103 is then inputted to an AND circuit 104 for outputting only a pulse signal S2 of a reproducing signal (which is called a clock pit reproducing signal in the following description) S1a corresponding to the clock pit shown in FIG. 32 by a window signal S3 from a decoder described later. The pulse signal S2 outputted from this AND circuit 104 is inputted to a phase comparator (which is called PD in the following description) 105. The PD 105 compares a phase of the inputted pulse signal S2 with the phase of a clock signal generated from a voltage control oscillator (which is called VCO in the following description) described later, and provides a difference between these phases.
The PD 105 outputs a phase difference signal according to the detected phase difference to a filter 106. This filter 106 outputs a voltage signal based on this phase difference signal to the VCO 107. The VCO 107 generates a clock signal having a predetermined phase until the voltage signal is inputted to this VCO 107 from the filter 106. However, when the voltage signal is inputted to the VCO 107 from the filter 106, this VCO 107 corrects the phase of a clock signal generated by this voltage signal and generates a recording/reproducing clock signal S4.
This recording/reproducing clock signal S4 is inputted to the A/D converter 101 and is also inputted to unillustrated demodulating circuit and tracking signal detecting circuit, etc. Further, this recording/reproducing clock signal S4 is inputted to a counter 108. This counter 108 counts the number of clock signals and outputs counting data indicative of a pit position to a decoder 109. The decoder 109 decodes the counting data from the counter 108 and outputs a window signal S3 to the AND circuit 104 at a predetermined timing. The decoder 109 also outputs a feedback signal S5 to the PD 105.
The recording/reproducing clock signal S4 inputted to the A/D converter 101 is set to a timing signal for determining the timing of an A/D conversion of the reproducing signal S1 inputted to the A/D converter 101. Accordingly, it is necessary to conform a phase of the recording/reproducing clock signal S4 to a phase of the clock pit reproducing signal S1a in a bottom (or peak) position thereof.
However, in the above conventional phase control circuit, no sampling signal can be obtained when an electric signal is missing by a defect in a memory medium, etc., in an area for writing the sampling signal. Accordingly, it is impossible to control the phase of a clock signal for reading data so that many errors in read data are caused.
In the conventional recording/reproducing timing generating circuit shown in FIG. 33, a phase of the recording/reproducing clock signal S4 is changed by a change in delay time of the pulsating circuit 102 and a change in stationary phase difference of the PLL circuit 103. Accordingly, it is difficult to accurately conform the phase of the recording/reproducing clock signal S4 to that of the clock pit reproducing signal S1a in the bottom (or peak) position thereof.
For example, as shown in FIG. 32, when the delay time of the pulsating circuit 102 is set to T1, the pulse signal S2 outputted from the pulsating circuit 102 is generated at a timing shifted by the time T1 from a bottom (or peak) position of the clock pit reproducing signal S1a.
When the stationary phase difference of the PLL circuit 103 is set to T2, the recording/reproducing clock signal S4 shown in FIG. 32 is generated at a timing shifted by the time T2 with respect to the pulse signal S2. Accordingly, the recording/reproducing clock signal S4 is generated at a timing shifted by the time T1+T2 from the bottom (or peak) position of the clock pit reproducing signal S1a.
A tracking error is obtained by calculating a difference in voltage level between reproducing signals S1 corresponding to two wobble pits. However, as shown in FIG. 32, when reproducing signals S1b corresponding to the two wobble pits are detected by the recording/reproducing clock signal S4 shifted by the time T1+T2, detecting timings of these reproducing signals S1b are equal to timings W1 and W2 shifted by the time T1+T2 from bottom (or peak) positions of the reproducing signals S1b. Accordingly, it is impossible to accurately detect a voltage level of each of the reproducing signals S1b.
Therefore, no tracking error can be accurately detected and no light spot can be positioned with respect to a target track. Further, it is impossible to accurately detect the reproducing level of a data pit recorded in a data area. Accordingly, when no phase of the recording/reproducing clock signal is in conformity with that of the clock pit reproducing signal in the bottom (or peak) position thereof, it is impossible to suitably record and reproduce information.